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Lattice Semiconductor
CSIX-to-PI40 IP Core User’s Guide
CSIX-to-PI40 Core Design Flow
The CSIX-to-PI40 IP Core can be implemented using various methods. The scope of this document covers only the
push-button Graphical User Interface (GUI) ?ow. Figure 13 illustrates the software ?ow model used when evaluat-
ing with the CSIX-to-PI40 core.
Figure 13. Lattice IP Core Evaluation Flow
Start
Install and launch ispLEVER software
Obtain desired IP package (download
Core Evaluation package or purchase
IP package)
Install IP package
Simulation
Model
IP Core Netlist
Perform functional simulation with
the provided core model
Synthesize top-level design with the
IP black box declaration
Place and route the design
Run static timing analysis
Done
IPexpress?
The Lattice IP con?guration tool, IPexpress, is incorporated in the ispLEVER ? software. IPexpress includes a GUI
for entering the required parameters to con?gure the core. For more information on using IPexpress and the
ispLEVER design software, refer to the software help and tutorials included with ispLEVER. For more information
on ispLEVER, see the Lattice web site at: www.latticesemi.com/software.
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